This package provides the Xilinx FPGA Unisim library as a set of VHDL snippets.
Xilinx FPGA Unsim libraries are or can be used to instantiate hardware dedicated logic elements available in the different FPGA families, elements such as PLL, MMCM , LUT, ...
Remark 1: This package replaces the "Xilinx-Snippets" package.
Remark 2: A similar extension for VScode can be found here
The list is not a complete copy of the Unisim library available in the Xilinx Vivado tool! It does not contain elements as PCIE, Ethernet MAC, transceivers or other because those elements are too big to instantiate and one will probably never instantiate these anyway because all of these components are typically used through a wizard. The wizard provides an instantiate-able model targeted and customised following what the user demanded through the wizard.
Select, up/down arrow keys or mouse, and click in the list the wanted component. For some components no list appears, then just hit [Tab] to instantiate the component.
When the IDDR is instantiated it appears as in below figure
Component labels are build this way:
The instantiated component label starts with FileName. Replace FileName with the name of the file, without extension, the component is instantiated. Naming instantiated components this way is done to easily find components in hierarchical designs. As showed the cursor is dropped on the highlighted FileName to allow one to change it easily. f the name can be kept, just hit [Tab].
The cursor jumps now to the second highlighted area, being 0. The is providing the amount of times the primitive is instantiated. Change it by typing a number or something else or leave it by hitting [Tab]
Hitting [Tab] makes the cursor jump from one port element to another allowing one to change the name of the connected signal or bus. After a signal or bus name is provided, hit [Tab] to jump to the next port.
Good catch. Let us know what about this package looks wrong to you, and we'll investigate right away.